1. Responsible for logic synthesis, formal verification, and static timing analysis of chips, and following up on backend feedback timing issues;

2. Collaborate with front-end engineers to develop SDC, develop DFT, and execute synthesis and DFT processes;

3. Work closely with the front-end design team and back-end engineers to integrate all chip SDC and develop back-end implementation plans;

4. Chip level timing eco and timing signoff acceptance, generating SDF and assisting the verification team in post simulation work;

5. Maintain synthesis/formal/sta related processes, automate s, check output quality at each stage, and work with the quality team to complete signoff;

6. Collaborate with the front-end design team to assist back-end engineers in conducting various physical checks and power consumption analysis;

7. Familiar with the generation of commonly used ATGP patterns;

8. Collaborate with backend engineers to solve various power domain related physical problems related to the frontend and backend based on low-power processes.

1. Bachelor's degree or above, with over 5 years of relevant work experience, truly responsible for the front-end and back-end work of mass-produced chips;

2. Proficient in Verilog language, mastering comprehensive processes and methods, full chip synthesis, and static timing analysis strategies;

3. Familiar with Shell/TCL/Peer/Python programs;

4. Possess the planning ability to implement Chip DFT, including scanning, boundary scanning, MemBIST, MemRepair, etc., and have a deep understanding of commonly used design for testability methods such as BIST, SCAN, JTAG, and ATPG;

5. Master and be familiar with static timing analysis and methods and strategies for timing convergence with the backend;

6. Have product level experience in back-end processes based on low-power power domain;

7. Familiarity with Cadence series backend tools is a good add-on.

1. Define the verification plan according to the design document;

2. Develop various validation models;

3. Conduct joint verification of MCU and RTL, including verification of application software and firmware;  

4. Develop module level validation components and support reusability for module level and system level validation;

5. FPGA verification and chip testing.

1. Bachelor's or Master's degree in Electronic Engineering, with 2-5 years of ASIC/SoC verification experience.  Experience in RTL design/modeling is preferred;  

2. Proficient in using UVM;

3. Proficient in system Verilog and various shell languages (Perl, CSH, TCL, SH, etc.);  

4. FPGA verification and chip verification experience is preferred;

5. Proficient in AMBA AHB/AXI/APB protocols, familiar with various commonly used peripherals such as 12C, UART, USB, etc;  

6. Have experience in SoC system design verification;

7. Familiar with microprocessors, DSP instruction sets, and how to integrate driver software into SoC systems;  

8. Familiar with HDL language, simulation tools, and testing platform design, assembly language, C or C++, ing language, etc.

1. Module level architecture definition and design;

2. Write design specifications and reports;

3. Module level RTL implementation;

4. SoC integration;

5. System and module level simulation and verification;  

6. Module level synthesis and timing analysis;

7. FPGA verification and chip testing of related modules;

8. Specification and architecture definition based on algorithm models.  

1. Bachelor's or Master's degree in Electronic Engineering, with 2-5 years of experience in digital design;

2. Solid knowledge of digital modular design (Data path, Filters, FIFO, etc.);  

3. Proficient in Verilog RTL coding, verification, and debugging;

4. SOC/FPGA design/verification experience;

5. Candidates with DFT work experience are preferred;  

6. Familiarity with System Verilog language is preferred;

7. Good communication skills, team spirit, and self motivation.

1. Overcoming technical challenges and breakthroughs in SoC system design and integration, including but not limited to system level module level simulation and verification, module level RTL implementation, module FPGA verification, and chip testing;

2. Define chip specifications and SoC architecture, module level architecture design, algorithm model-based specifications and architecture definitions;

3. Evaluate and optimize the performance, area, and power consumption of chips based on product requirements;

4. Guide the team to complete functional validation, timing optimization, post silicon testing, product application import, and mass production maintenance.  

1. More than 10 years of experience in chip design, with experience as a chiplev leader leading chip project chip fabrication; 

2. Familiar with communication protocols and the design, production, quality control, reliability, and other related knowledge of communication chip ICs. Experience in NB-IOT and CAT1 product development is preferred;  

3. Familiar with SoC architecture and top-level interfaces, able to conduct IP evaluation, design implementation, and top-level integration based on design specifications;  4. Priority will be given to those with outstanding abilities in either Mode/STA/DFT;  

5. Possess strong abilities in problem analysis and promotion, as well as innovative technical methodology;  

6. Possess mature project coordination and risk prediction abilities, excellent team collaboration experience, and strong endurance and perseverance.

1. Independently complete layout design and arrange layout and wiring reasonably;

2. Responsible for writing and archiving project related documents;  

3. Complete other tasks assigned by the department leader. 

1. Bachelor's degree or above, 4-5 years of layout experience, major in electronics or related fields;

2. Familiar with analog circuits, integrated circuit processes, transistor principles, with module level experience, including RF (LNA, Mixer, PA, PLL) analog circuits (AD, DA, filter, PMU), as well as top-level experience;  

3. Proactive and proactive in work, with good learning ability, communication skills, and team spirit.